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After the preparation of my Ph.D. thesis (with a CIFRE funding) within the
Real Time Systems research team at the
IRCCyN lab,
I am currently working as a R&D (doctor-)engineer for
Sodius, the industrial partner of my Ph.D.
| Address: |
Sodius
6 rue de Cornouaille
BP 91941
44319 Nantes CEDEX 03
France |
| Phone: |
+33 2 28 23 60 60 |
| Fax: |
+33 2 28 23 60 57 |
| E-mail: |
cseidner@no-spam-sodius.com
(remove no-spam-)
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My main research interests lie in the formal simulation and verification of some models used in
Systems Engineering
(SE) for the description and design of functional architectures. My research themes include, for instance:
- the formalization and simulation of EFFBDs
(Enhanced Functional Flow Block Diagrams),
a language widely used in SE for the modeling of functional architectures;
- the model checking of safety engineering properties on EFFBDs;
- the model checking of TCTL (Timed Computation Tree Logic) on time Petri nets;
- model transformation through the MDA/MDE (Model Driven Architecture/Engineering) approach.
On November 3rd 2009, I defensed my Ph.D. thesis, entitled
EFFBDs Verification: Model checking in Systems Engineering.
The members of the defense jury were:
- Charles André (chair),
professor, University of Nice Sophia Antipolis (I3S);
- Fabrice Kordon (rapporteur),
professor, P. & M. Curie University (LIP6);
- François Vernadat (rapporteur),
professor, INSA Toulouse (LAAS);
- Éric Niel (examiner),
professor, INSA Lyon (Ampère);
- Olivier (H.) Roux (advisor),
associate professor, University of Nantes (IRCCyN);
- Jean-Philippe Lerat (examiner),
sodius C.E.O;
- Jean-Luc Wippler (invited),
System engineer at C-S.
The dissertation is available here and on
HAL (French only);
the defense slides are here.